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V62C1162048L(L)
Ultra Low Power 128K x 16 CMOS SRAM
Features
* Low-power consumption - Active: 35mA ICC at 70ns - Stand-by: 10 A (CMOS input/output) 2 A (CMOS input/output, L version) * 70/85/100/120 ns access time * Equal access and cycle time * Single +1.8V to2.2V Power Supply * Tri-state output * Automatic power-down when deselected * Multiple center power and ground pins for improved noise immunity * Individual byte controls for both Read and Write cycles * Available in 44 pin TSOPII / 48-fpBGA / 48-BGA
Functional Description
The V62C1162048L is a Low Power CMOS Static RAM organized as 131,072 words by 16 bits. Easy Memory expansion is provided by an active LOW (CE) and (OE) pin. This device has an automatic power-down mode feature when deselected. Separate Byte Enable controls (BLE and BHE) allow individual bytes to be accessed. BLE controls the lower bits I/O1 - I/O8. BHE controls the upper bits I/O9 - I/O16. Writing to these devices is performed by taking Chip Enable (CE) with Write Enable (WE) and Byte Enable (BLE/BHE) LOW. Reading from the device is performed by taking Chip Enable (CE) with Output Enable (OE) and Byte Enable (BLE/BHE) LOW while Write Enable (WE) is held HIGH.
Logic Block Diagram
Pre-Charge Circuit
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
TSOPII / 48-fpBGA / 48-BGA (See nest page)
A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC
Row Select
Vcc Vss
Memory Array 1024 X 2048
I/O1 - I/O8 I/O9 - I/O16
Data Cont Data Cont
I/O Circuit Column Select
A10 A11 A12 A13 A14 A15 A16
WE OE
BHE BLE CE
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REV. 1.2 May 2001 V62C1162048L(L)
V62C1162048L(L)
MOSEL VITELIC V62C1162048L(L)M
1 2 3 4 5 6 1 2 3 4 5 6
A
BLE
OE
A0
A1
A2
NC
B
I/O9
BHE
A3
A4
CE
I/O1
C
I/O10
I/O11
A5
A6
I/O2
I/O3
D
VSS
I/O12
NC
A7
I/O4
VCC
E
VCC
I/O13
NC
A16
I/O5
VSS
F
I/O15
I/O14
A14
A15
I/O6
I/O7
G H
I/O16 NC
NC A8
A12 A9
A13 A10
WE A11
I/O8 NC
Note: NC means no Ball.
Top View
Top View
48 Ball - 6 x 8 BGA (Ultra Low Power)
C A1
PACKAGE OUTLINE DWG.
SYMBOL A
UNIT:MM 1.10+0.10 0.22+0.05 0.35 0.36(TYP) 8.00+0.10 5.25 6.00+0.10 3.75 0.75TYP 0.10
A
aaa
SIDE VIEW
A1 b c
D D1
D D1 E
6
e
E1 e
5
aaa
4
E1 E
3
2
1 A B C D E F G H
BOTTOM VIEW
b SOLDER BALL
2
REV. 1.2 May 2001 V62C1162048L(L)
V62C1162048L(L)
Absolute Maximum Ratings * Parameter
Voltage on Any Pin Relative to Gnd Power Dissipation Storage Temperature (Plastic) Temperature Under Bias
Symbol
Vt PT Tstg Tbias
Minimum
-0.5 - -55 -40
Maximum
+4.0 1.0 +150 +85
Unit
V W
0
C
0C
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth Table
CE OE WE BLE BHE I/O1-I/O8 I/O9-I/O16 Power Mode
H L L L L L L L L
X L L L X X X H X
X H H H L L L H X
X L H L L L H X H
X H L L L H L X H
High-Z Data Out High-Z Data Out Data In Data In High-Z High-Z High-Z
High-Z High-Z Data Out Data Out Data In High-Z Data In High-Z High-Z
Standby Active Active Active Active Active Active Active Active
Standby Low Byte Read High Byte Read Word Read Word Write Low Byte Write High Byte Write Output Disable Output Disable
* Key: X = Don't Care, L = Low, H = High
Recommended Operating Conditions (TA = 0oC to +70oC / -40oC to 85oC**) Parameter
Supply Voltage
Symbol
VCC Gnd VIH VIL
Min
1.8 0.0 1.6 -0.5*
Typ
2.0 0.0 -
Max
2.2 0.0 VCC + 0.2 0.4
Unit
V V V V
Input Voltage
* VIL min = -2.0V for pulse width less than tRC/2. ** For Industrial Temperature
3
REV. 1.2 May 2001 V62C1162048L(L)
V62C1162048L(L)
DC Operating Characteristics (Vcc =1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Parameter
Input Leakage Current Output Leakage Current Operating Power Supply Current Average Operating Current
Sym
Test Conditions
Vcc = Max, Vin = Gnd to Vcc CE = VIH or Vcc= Max, VOUT = Gnd to Vcc CE = VIL , VIN = VIH or VIL , IOUT = 0 IOUT = 0mA, Min Cycle, 100% Duty CE < 0.2V IOUT = 0mA,
Cycle Time=1s, Duty=100%
-70
1 1 5 35 3 -
-85
1 1 5 35 3
-100
1 1 5 30 3
-120
1 1 5 30 3
Min Max Min Max Min Max Min Max
Unit
A A
mA
IILII IILOI
ICC ICC1 ICC2
mA mA
Standby Power Supply Current (TTL Level) Standby Power Supply Current (CMOS Level) Output Low Voltage Output High Voltage
ISB ISB1
CE = VIH CE > Vcc - 0.2V VIN < 0.2V or VIN > Vcc- 0.2V IOL = 2 mA IOH = -1 mA
-
0.5 10 2 0.4 -
1.6
0.5 10 2 0.4 -
1.6
0.5 10 2 0.4 -
1.6
0.5 10 2 0.4 -
mA
A A
V V
L
1.6
VOL VOH
Capacitance (f = 1MHz, TA = 250C) Parameter*
Input Capacitance I/O Capacitance
Symbol
Cin CI/O
Test Condition
Vin = 0V Vin = Vout = 0V
Max
7 8
Unit
pF pF
* This parameter is guaranteed by device characterization and is not production tested.
AC Test Conditions Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load Condition 70ns/85ns Load for 100ns/120ns
0.4V to 1.6V 5ns 1.0V
CL*
TTL
CL = 30pf + 1TTL Load CL = 100pf + 1TTL Load
Figure A.
* Including Scope and Jig Capacitance
4
REV. 1.2 May 2001 V62C1162048L(L)
V62C1162048L(L)
Read Cycle (9) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Output Hold from Address Change Chip Enable to Output in Low-Z Chip Disable to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z BLE, BHE Enable to Output in Low-Z BLE, BHE Disable to Output in High-Z BLE, BHE Access Time
Sym
tRC tAA tACE tOE tOH tLZ tHZ tOLZ tOHZ tBLZ tBHZ tBA 70 10 10 5 5 -
-70
70 70 40 30 25 25 40 85 10 10 5 5 -
-85
85 85 40 35 30 30 40
-100
100 10 10 5 5 100 100 50 40 35 35 50
-120
120 10 10 5 5 120 120 60 45 40 40 60
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
Note
Min Max Min Max Min Max Min Max
4,5 3,4,5
4,5 3,4,5
Write Cycle (11) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter
Write Cycle Time Chip Enable to Write End Address Setup to Write End Address Setup Time Write Pulse Width Write Recovery Time Data Valid to Write End Data Hold Time Write Enable to Output in High-Z Output Active from Write End BLE, BHE Setup to Write End
Symbol
tWC tCW tAW tAS tWP tWR tDW tDH tWHZ tOW tBW 70 60 60 0 50 0 30 0 5 60
-70
30 5 85 70 70 0 60 0 35 0 5 70
-85
35 -
-100
100
-120
120 90 90 0 80 0 45 0 5 90 45 -
Unit
ns ns ns ns ns ns ns ns ns ns ns
Note
Min Max Min Max Min Max Min Max
80 80 0 70 0 40 0 5 80
40 -
REV. 1.2 May 2001 V62C1162048L(L)
V62C1162048L(L)
Timing Waveform of Read Cycle 1 (Address Controlled)
tRC
Address
tOH
Data Out
tAA Data Valid
Previous Data Valid
Timing Waveform of Read Cycle 2
tRC
Address
tAA CE tACE tLZ(4,5) tBA tBLZ(4,5) tOE High-Z tOLZ
tHZ(3,4,5) tBHZ(3,4,5)
(BLE/BHE)
tOHZ tOH Data Valid
OE Data Out
Notes (Read Cycle) 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels. 4. At any given temperature and voltage condition tHZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CE = VIL. 7. Address valid prior to coincident with CE transition Low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. For test conditions, see AC Test Condition, Figure A.
6
REV. 1.2 May 2001 V62C1162048L(L)
V62C1162048L(L)
Timing Waveform of Write Cycle 1 (Address Controlled)
tWC
Address
tAW
CE BLE/BHE
tCW (3) tBW
tWR (5)
tAS (4)
WE
tWP (2) tDW tDH tOW
Data In Data Out
High-Z
tOHZ (6)
High-Z (8)
Timing Waveform of Write Cycle 2 (CE Controlled)
tWC
Address
tAW
CE BLE/BHE
tCW (3)
tWR (5)
tAS (4)
tBW tWP (2)
WE
tDW
Data In Data Out
High-Z
tDH
High-Z
tLZ
tWHZ (6)
High-Z (8)
Timing Waveform of Write Cycle 3 (BLE/BHE Controlled)
tWC
Address
tAW
CE
tCW (3)
tWR (5)
tAS (4)
BLE/BHE
tBW tWP (2)
WE
tDW
Data In Data Out
High-Z
tDH
High-Z
tBLZ
tWHZ (6)
High-Z (8)
REV. 1.2 May 2001 V62C1162048L(L)
7
V62C1162048L(L)
Notes (Write Cycle)
All write timing is referenced from the last valid address to the first transition address. A write occurs during the overlap of a low CE and WE. A write begins at the latest transition among CE and WE going low: A write ends at the earliest transition among CE going high and WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CE going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. 6. If OE, CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should not be applied. 11. For test conditions, see AC Test Condition, Figure A. 1. 2.
8
REV. 1.2 May 2001 V62C1162048L(L)
V62C1162048L(L)
Data Retention Characteristics (L Version Only)(1) Parameter
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time(2)
Symbol
VDR ICCDR tCDR tR
Test Condition
CE > VCC - 0.2V
Min
1.0 -
Max
-
Unit
V A ns ns
1 -
VIN > VCC - 0.2V or VIN < 0.2V
0 tRC
Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C)
Data Retention Mode
VCC
Vcc_typ V DR > 1.0V Vcc_typ
tCDR CE
V DR
tR
V IH
V IH
Notes (Write Cycle)
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. L-version includes this feature. This Parameter is samples and not 100% tested. For test conditions, see AC Test Condition, Figure A. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. This parameter is guaranteed, but is not tested. WE is High for read cycle. CE and OE are LOW for read cycle. Address valid prior to or coincident with CE transition LOW. All read cycle timings are referenced from the last valid address to the first transtion address. CE or WE must be HIGH during address transition. All write cycle timings are referenced from the last valid address to the first transition address.
9
REV. 1.2 May 2001 V62C1162048L(L)
V62C1162048L(L)
Ordering Information
Device Type* V62C1162048L-70T V62C1162048L-85T V62C1162048L-100T V62C1162048L-120T V62C1162048LL-70T V62C1162048LL-85T V62C1162048LL-100T V62C1162048LL-120T V62C1162048L(L)-70B V62C1162048L(L)-85B V62C1162048L(L)-100B V62C1162048L(L)-120B V62C1162048L(L)-70M V62C1162048L(L)-85M V62C1162048L(L)-100M V62C1162048L(L)-120M Speed 70 ns 85 ns 100 ns 120 ns 70 ns 85 ns 100 ns 120 ns 70 ns 85 ns 100 ns 120 ns 70 ns 85 ns 100 ns 120 ns 48-fpBGA Package 44-pin TSOP Type 2
48-BGA
* For Industrial temperature tested devices, an "I" designator will be added to the end of the device number.
10
REV. 1.2 May 2001 V62C1162048L(L)
MOSEL VITELIC
U.S.A.
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
WORLDWIDE OFFICES
TAIWAN
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V62C1162048L(L)
UK & IRELAND
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JAPAN
ONZE 1852 BUILDING 6F 2-14-6 SHINTOMI, CHUO-KU TOKYO 104-0041 PHONE: 03-3537-1400 FAX: 03-3537-1402
GERMANY (CONTINENTAL EUROPE & ISRAEL)
BENZSTRASSE 32 71083 HERRENBERG GERMANY PHONE: +49 7032 2796-0 FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952
SOUTHWESTERN
302 N. EL CAMINO REAL #200 SAN CLEMENTE, CA 92672 PHONE: 949-361-7873 FAX: 949-361-7807
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(c) Copyright 2001, MOSEL VITELIC Inc.
5/01 Printed in U.S.A.
The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

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